The present invention relates to a digital analog converter for use in digital audio equipments such as compact disk (CD) players and digital audio tape (DAT) recorders. More particularly, the present invention relates to a digital analog converter having improved low-level output signal error.
Digital to analog converter circuits are generally manufactured to provide a nonlinear output error of no more than + or -1/2 LSB (least significant bit). However, DAC's used in audio equipments often do not meet that standard because of the weighting error in their more significant bits even though some correction is possible by means of laser trimming. While some error correction is possible, the DAC's presently in use are influenced by ambient external conditions such as temperature and humidity. At present, DAC's meeting the + or -1/2 LSB resolution requirement resolve only 14-16 bits or less.
To simplify circuit structure, most of the DAC's used in audio equipments are unipolar made bipolar by adding midpoint offsets to their outputs. In some equipments, because input data represent audio signals, data output as unipolar are made bipolar by capacitors or servo circuits that remove DC offsets from the analog outputs.
A DAC with improved error characteristics for low outputs is proposed in Japanese Laid Open Patent Publication No. 61-242421 (U.S. Pat. No. 4,727,355). This DAC, called a floating or exponent DAC, consists of data shift circuits, a mantissa DAC, exponent DAC's and so on. According to this DAC, low-level output error can be decreased by using a mantissa DAC to D/A convert the data while shifting it to more significant bits in accordance with the level of the analog signals represented by the digital data. However, the structure of the proposed DAC is complex and because the proposed DAC is a two step converter (an exponent digital to analog converter made to convert the output signals of a mantissa DAC), a glitch is inserted into the output analog signal. A glitch is defined as an undesired voltage spike occurring on a signal being DA converted. A glitch can occur, for example, on a major carry, such as when switching from 0111111111 to 1000000000 because there is an interim condition in which all bits are 0.